It is known from “Frequent Value Encoding For Low Power Data Buses” Jun Yang et al, ACM (Association for Computing Machinery) Transactions on Design Automation of Electronic Systems, Volume 9, No. 3, July 2004, Pages 354 to 384 to encode data values to be transmitted to reduce switching activity on external buses for the purpose of reducing power consumption. However, this technique has the disadvantage that extra circuit resources and power are consumed by first encoding the data values to be transmitted and then subsequently decoding these values. This reduces the benefit achieved. Furthermore, the increased gate count represents a cost and complexity overhead which is disadvantageous. In addition, the requirement for changes in both the sender of the data and the receiver of the data has practical difficulties when those entities might be provided by different sources and, for example, changes within the receiver may not be readily made so as to provide appropriate decoding. Also, a separate decoder with its own bus drivers consumes significant power.
It is known from “Reordering Memory Bus Transactions For Reduced Power Consumption” Bruce R. Childers et al. ACM SIGPLAN Workshop On Languages, Compilers, and Tools for Embedded Systems, during ACM SIGPLAN Conference On Programming Language Design and Implementation (PLDI'2000, June 2000) to examine with hardware the data words within a cache line being transferred to or from memory so as to determine a different order for the data words to be transferred in order to reduce switching activity and accordingly energy consumption. This approach of examining the individual data words to be transmitted so as to calculate a new order of transmission which reduces the Hamming distances between elements has the disadvantage of requiring a considerable amount of special purpose hardware so that it can be achieved sufficiently rapidly. This additional hardware consumes power which detracts from the energy saved by reducing the switching activity on the buses. The additional hardware is also a disadvantageous complexity and cost overhead.
It will be appreciated from the above that there is a desire to reduce the power consumption associated with the switching of signal lines when transmitting data over a data bus. These signal lines, particularly when they are off-chip such as between an integrated circuit and an associated separate memory integrated circuit (IC), have a relatively high capacitance and so soak up a disadvantageous amount of energy to drive from one signal level to another signal level at high speed. In a typical present day system driving the memory bus for an off-chip memory subsystem might consume 15 to 30% of the overall system power consumption. Measures which can reduce this power consumption, and yet not introduce their own unacceptable disadvantages, are strongly advantageous.